1. Field of the Invention
The present invention relates in general to a charge coupled device (CCD) image sensor, and more particularly to a CCD image sensor having a plurality of vertical charge coupled devices (VCCDs) each formed in a zig-zag pattern in a vertical direction and a plurality of groups of photodiodes, the photodiodes of the respective groups being arranged respectively on the left and right sides of each of the VCCDs, so that an improvement in resolution of a picture can be made in the same chip size.
2. Description of the Prior Art
Generally, a CCD is believed to be an active device for transferring under a control of a clock pulse a signal charge corresponding to incident light incoming along a predetermined path and has typically been used in image processing devices, such as, for example, a storage device, a logic element, a CCD image sensor and etc..
The scanning of the CCD image sensor employing the CCD is typically of an interlaced scanning type and a non-interlaced scanning type.
In the non-interlaced scanning, there are provided frames each containing a plurality of fields, the scanning on the screen being in sequence performed beginning with data in the first input field. On the other hand, in the interlaced scanning, there are provided frames each containing a plurality of even fields and a plurality of odd fields, the scanning on the screen being in turn performed beginning with data in the odd field.
Therefore, in the non-interlaced scanning, the scanning rate is fast such that the actual image of a fast moving object can be picked up accurately. For this reason, the non-interlaced scanning may be applied to a military equipment, such as a missile.
However, a problem with this non-interlaced scanning is that the image shakes on the screen.
For the interlaced scanning, there is provided a sense of stability of the image in that the scanning rate is slower than that in the non-interlaced scanning, but a fast moving object appears as two images. For this reason, the interlaced scanning is inappropriate to a military purpose and typically applied to a television broadcasting system, such as a NTSC system or a PAL system, for the scanning of image on the screen.
An example of a conventional CCD image sensor of the interlaced scanning type will now be mentioned with reference to FIGS. 1 through 4.
Referring to FIG. 1, there is shown a schematic diagram of a construction of the conventional CCD image sensor of the interlaced scanning type. The conventional CCD image sensor comprises a plurality of vertical charge coupled device (VCCD) regions VCCD arranged at a constant interval in a horizontal direction with respect to one another, each of the VCCD regions VCCD being extended to a desired length in a vertical direction, a plurality of groups of photodiodes PD each for generating a signal charge in response to incident light, the photodiodes PD of the respective groups being arranged at one side of each of the VCCD regions VCCD and at a constant interval in the vertical direction with respect to one another, a horizontal charge coupled device (HCCD) region HCCD for transferring in the horizontal direction the signal charges which are transferred from the photodiodes PD through the VCCD regions VCCD thereto, and a sensing amplifier AMP for converting the signal charges from the HCCD region HCCD into voltage information and outputting the voltage information externally.
Referring to FIG. 2, there is shown a layout diagram of the construction of the conventional CCD image sensor in FIG. 1. As shown in this figure, transfer gates TG are provided to transfer the signal charges from the photodiodes PD to the VCCD regions VCCD. Since each of the frames contains the two fields or odd and even fields, each of the transfer gates TG consists of two transfer gates TG1 and TG2 corresponding respectively to the odd and even fields. The first transfer gates TG1 are provided to transfer to the VCCD regions VCCD the signal charges from the photodiodes PD1 arranged in the odd order in the vertical direction in the odd fields or arranged on the odd horizontal scanning lines and the second transfer gates TG1 are provided to transfer to the VCCD regions VCCD the signal charges from the photodiodes PD2 arranged in the even order in the vertical direction in the even fields or arranged on the even horizontal scanning lines.
Transfer gate electrodes PG1 and PG2 are connected respectively to the first and second transfer gates TG1 and TG2 such that the signal charges from the photodiodes PD are transferred to the VCCD regions VCCD in response to VCCD clock signals V.phi.1-V.phi.4 of four phases which are applied respectively to the transfer gate electrodes PG1 and PG2, one clock signal corresponding to one phase.
FIG. 3a is a sectional view, taken on the line a--a' of FIG. 2, which illustrates portions in which the transfer gates are formed and FIG. 3b is a sectional view, taken on the line b--b' of FIG. 2B, which illustrates portions in which the transfer gates are not formed. The conventional CCD image sensor comprises a N type substrate 100 and a P type well 200, formed on the N type substrate 100. The N type photodiodes PD and the N type VCCD regions VCCD are, in turn, successively arranged on the N type substrate 100, with adjacent ones of the photodiodes PD and VCCD regions VCCD being isolated from each other at a desired interval via a channel stop region ST. On the surface of each of the N type photodiodes PD is formed a P.sup.+ type thin layer 300 for application of an initial bias voltage. Herein, the P type well 200 is comprised of two types of wells, a shallow P type well 200a and a deep P type well 200b, for control of over flow drain (OFD) voltage, the shallow P type well 200a being formed under each of the N type photodiodes PD and the deep P type well 200b being formed under each of the N type VCCD regions VCCD.
In FIG. 3a, a first transfer gate electrode PG1b of the transfer gate electrode PG1 is formed over the N type VCCD region VCCD and the channel stop region ST for application of the first clock signal V.phi.1. The first transfer gate TG1 is connected to the first transfer gate electrode PG1b for connection of the photodiode PD with the VCCD region VCCD therethrough.
In FIG. 3b, a second transfer gate electrode PG1a of the transfer gate electrode PG1 is formed over the N type VCCD region VCCD and the channel stop region ST for application of the second clock signal V.phi.2. The photodiode PD and VCCD region VCCD are isolated from each other at a desired interval via the channel stop region ST.
FIG. 4a is a timing diagram of the VCCD clock signals V.phi.1-V.phi.4 which are applied respectively to the transfer gate electrodes PG1 and PG2, FIG. 4b is a pulse waveform diagram of the VCCD clock signals V.phi.1-V.phi.4 at the unit interval K of FIG. 4a and FIG. 4c is a pixel format of one picture, or one frame in the conventional CCD image sensor of the interlaced scanning type.
The operation of the conventional CCD image sensor of the above-mentioned construction will hereinafter be described.
In operation, upon receiving the incident light, the photodiodes PD generate the signal charges in proportion to an intensity of the light. The generated signal charges are transferred to the VCCD regions VCCD in response to the VCCD clock signals V.phi.1-V.phi.4 which are applied to the transfer gate electrodes PG1 and PG2. In other words, in the odd fields, a voltage V1 of high level is applied to the first transfer gates TG1 by the VCCD clock signals V.phi.1 and V.phi.2 which are applied to the transfer gate electrodes PG1. As a result, transferred to the VCCD regions VCCD are the signal charges generated from the photodiodes PD1 arranged on the odd horizontal scanning lines. On the other hand, in the even fields, a voltage V2 of high level is applied to the second transfer gates TG2 by the VCCD clock signals V.phi.3 and V.phi.4 which are applied to the transfer gate electrodes PG2. As a result, transferred to the VCCD regions VCCD are the signal charges generated from the photodiodes PD2 arranged on the even horizontal scanning lines.
The signal charges transferred to the VCCD regions VCCD are then transferred to the HCCD region HCCD, which feeds the transferred signal charges to the sensing amplifier AMP in response to a HCCD clock signal applied thereto. Finally, the sensing amplifier AMP converts the signal charges from the HCCD region HCCD into voltage information and outputs the voltage information externally.
The image signals outputted in this manner are arranged in a form as shown in FIG. 4c. Namely, the image signals outputted upon application of the voltage V1 of high level to the first transfer gates TG1 in the odd fields are arranged at the positions designated by "1" and the image signals outputted upon application of the voltage V2 of high level to the second transfer gates TG2 in the even fields are arranged at the positions designated by "2".
However, the above-mentioned conventional CCD image sensor of the interlaced scanning type has a disadvantage, in that the photodiodes are arranged at only one side of the VCCD regions, thereby resulting in a low resolution of the picture. A prior art attempt to extend the areas of the photodiodes to enhance the resolution of the picture has a difficulty in the same chip size since the areas of the photodiodes are restricted by the VCCD regions. For this reason, the prior art attempt cannot be accomplished without an increase in the chip size.